作者: Abhijeet Ashok Chachad , Dheera Balasubramanian , Roger Kyle Castille , Joseph Raymond Michael Zbiciak
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摘要: This invention is a data processing system having multi-level cache system. The includes at least first level and second cache. Upon miss in both the one evicts allocates line within determine from address whether request falls low half or high of allocated line. requests external memory receipt supplied to CPU. then for other