Method And Apparatus For A Zero Voltage Processor
作者： Robert Milstrey , Sanjeev Jahagirdar , Stephen A. Fischer , Shai Rotem , Alon Naveh
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摘要: Embodiments of the invention relate to a method and apparatus for zero voltage processor sleep state. A may include dedicated cache memory. regulator be coupled provide an operating processor. During transition power management state processor, operational applied by reduced approximately variables associated with saved
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