Computer-Aided Design Techniques for Low Power Sequential Logic Circuits

作者: Srinivas Devadas , Jose Monteiro

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摘要: 1 Introduction.- 1.1 Power as a Design Constraint.- 1.2 Organization of this Book.- References.- 2 Estimation.- 2.1 Dissipation Model.- 2.2 Switching Activity 2.2.1 Simulation-Based Techniques.- 2.2.2 Issues in Probabilistic Estimation 2.2.3 2.3 Summary.- 3 A Method for Combinational Circuits.- 3.1 Symbolic Simulation.- 3.2 Transparent Latches.- 3.3 Modeling Inertial Delay.- 3.4 Results.- 3.5 4 Sequential 4.1 Pipelines.- 4.2 Finite State Machines: Exact Method.- 4.2.1 Temporal Correlation.- 4.2.2 Probability Computation.- 4.2.3 given Probabilities.- 4.3 Approximate 4.3.1 Basis the Approximation.- 4.3.2 Computing Present Line 4.3.3 Picard-Peano 4.3.4 Newton-Raphson 4.3.5 Improving Accuracy using m-Expanded Networks.- 4.3.6 k-Unrolled 4.3.7 Redundant Lines.- 4.4 Results on 4.5 Correlation Input Sequences.- 4.5.1 Completely and Incompletely Specified 4.5.2 Assembly Programs.- 4.5.3 Experimental 4.6 5 Optimization Techniques Low 5.1 by Transistor Sizing.- 5.2 Logic Level Optimization.- 5.2.1 Path Balancing.- 5.2.2 Don't-care 5.2.3 Factorization.- 5.2.4 Technology Mapping.- 5.3 5.3.1 Encoding.- 5.3.2 Encoding Datapath.- 5.3.3 Gated Clocks.- 5.4 6 Retiming Power.- 6.1 Review Retiming.- 6.1.1 Basic Concepts.- 6.1.2 Applications 6.2 6.2.1 Cost Function.- 6.2.2 Verifying Given Clock Period.- 6.2.3 Constraints.- 6.2.4 Executing 6.3 6.4 Conclusions.- 7 Precomputation.- 7.1 Subset Disabling 7.1.1 Precomputation Architecture.- 7.1.2 An Example.- 7.1.3 Synthesis Logic.- 7.1.4 Multiple-Output Functions.- 7.1.5 Examples Applied to Datapath Modules.- 7.1.6 Multiple Cycle 7.1.7 7.2 Complete 7.2.1 7.2.2 7.2.3 7.2.4 Simplifying Original Block.- 7.2.5 7.2.6 7.3 7.3.1 7.3.2 at Inputs.- 7.3.3 Arbitrary Sub-Circuits Circuit.- 7.3.4 7.4 Multiplexor-Based 7.5 8 High-Level 8.1 Register Transfer 8.1.1 Functional 8.1.2 Controller.- 8.1.3 Interconnect.- 8.2 Behavioral 8.2.1 Transformation 8.2.2 Scheduling 8.2.3 Allocation 8.2.4 Optimizations Register-Transfer Level.- 8.3 9 Conclusion.- 9.1 9.2 9.3 RT References.

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