Predictive snooping of cache memory for master-initiated accesses

摘要: When a PCI-bus controller receives request from master to transfer data with an address in secondary memory, the performs initial inquire cycle and withholds TRDY# until any write-back completes. The then allows burst access take place between memory master, simultaneously predictively, of L1 cache for next line. In this manner, if PCI continues past line boundary, new will already have taken place, or be progress, thereby allowing proceed with, at most, short delay. Predictive snoop cycles are not performed first would last before boundary is reached.