A High-Speed DES Implementation for Network Applications

作者: Hans Eberle

DOI: 10.1007/3-540-48071-4_37

关键词:

摘要: A high-speed data encryption chip implementing the Data Encryption Standard (DES) has been developed. The DES modes of operation supported are Electronic Code Book and Cipher Block Chaining. is based on a gallium arsenide (GaAs) gate array containing 50K transistors. At clock frequency 250 MHz, can be encrypted or decrypted at rate 1 GBit/second, making this fastest single-chip implementation reported to date. High performance high density have achieved by using custom-designed circuits implement core algorithm. These employ precharged logic, methodology novel design GaAs devices. pipelined flow-through architecture an efficient key exchange mechanism make suitable for low-latency network controllers.

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