An MDE approach for modeling network on chip topologies

摘要: Network on Chip (NoC) is a research field path that primarily addresses the global communication in System (SoC).The selected topology of components interconnects plays prime role performance NoC architecture, for conception, high-level synthesis approaches are utilized thus behaviorally description system refined into an accurate register-transfer-level (RTL) design SoC implementation. In recent MARTE (Modeling and Analysis Real-time Embedded Systems) Profile, notion multidimensional multiplicity has been proposed to model repetitive structures topology. This paper presents contribution new methodology modeling based Model Driven Architecture Modeling Real-Time embedded (MARTE), it aims prove effectiveness standard irregular or globally locally regular architectures. We will start this work by high level abstraction reach low through generated VHDL code.