作者: Lianyong Dong , Qiang Dou , Quanyou Feng , Wenhua Dou
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摘要: The Data Vortex switch architecture has been proposed as a scalable low-latency all-optical path interconnection fabric for packet switches. To facilitate optical implementation, the employs cylinder hierarchical topology, synchronous timing and deflection routing that act to reduce necessary logic operations buffering. angle parameter of A, significant impact on accepted traffic average latency. This paper provides comparison study two architectures with A=1 A >1 (here A=4) under asymmetric input/output (I/O) mode, focusing resulting performance in results show that, same size, performs better various patterns by providing more "virtual buffers".