Cam with additional row cells connected to match line

作者: Anthony I. Stansfield , Catherine L. Barnaby , Richard J. Gammack

DOI:

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摘要: A method of accessing a content addressable memory having plurality RAM cells connected in an array rows and columns, each row for storing data word, at least one additional cell checking bit match line providing signal to indicate when occurs between input word stored cells, which comprises the said additonal row, value dependent on accordance with error system, controlling system effect associate operation by inputting columns same comparing contents any where mismatch causing two that change level being arranged operate time delay is less than required single mismatch. The invention also provides memory.

参考文章(11)
Mark R. Waggoner, Ramin Shirani, Daniel J. Cimino, Edwin Z. DeSouza, First-in, first-out memory circuit ,(1992)
Takeshi Nakayama, Kazuo Kobayashi, Yasushi Terada, Masanori Hayashikoshi, Yoshikazu Miyawaki, Semiconductor memory device having error correcting function ,(1990)
Takeshi Nakayama, Kazuo Kobayashi, Yasushi Terada, Nonvolatile content-addressable memory and operating method therefor ,(1989)
Hideaki Arima, Kiyoto Watabe, Yuichi Nakashima, Natsuo Ajika, Takahisa Eimori, Shinichi Satoh, Hirofumi Shinohara, Content addressable memory device ,(1989)
Taisheng Feng, Jennifer Y. Chiao, Richard D. Crisp, Cache memory with a parity write control circuit ,(1990)
Masaaki Mihara, Takeshi Hamamoto, Toshifumi Kobayashi, Content addressable memory combining match comparisons of a plurality of cells ,(1990)
Kousuke Takahashi, Hachiro Yamada, Content-addressable memory ,(1985)