作者: N.G. Bourbakis , A. Mogzadeh , S. Mertoguno , C. Koutsougeras
DOI: 10.1109/TSMCA.2002.805765
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摘要: This paper presents a method of knowledge representation for very large scale integration (VLSI) chip design which provides the necessary information abstraction from physical to gate-level logic through high-level behavioral model. The scheme used by ANTISTROFEAS system utilizes hierarchical attributed graph structure consists incrementally abstracted VLSI system. is well-suited reverse-engineering chips layer mask layout data, but also applicable applications at many levels process including rule checking, synthesis, verification, and partitioning-compaction problems. any technology, designed take advantage artificial intelligence. expert techniques, disassociating manipulation data rules govern its correctness transformation other usage.