Logic Synthesis and Verification Algorithms

摘要: From the Publisher: Logic Synthesis and Verification Algorithms blends mathematical foundations algorithmic developments with circuit design issues. Each new technique is presented in context of its application to design. Through study optimal two-level multilevel combinational design, reader introduced basic concepts, such as Boolean algebra, local search, algebraic factorization. Similarly, through sequential graph algorithms, finite state systems, language theory. Throughout book, recurrent themes branch bound, dynamic programming, symbolic implicit enumeration are used establish principles. Circuit designers CAD tool developers alike will find Logic useful an introductory reference text. The rich collection examples solved problems make this book ideal for self study. Because careful balance theory application, serve well a textbook upper division first year graduate students electrical computer engineering.