Fault tolerant Four-State Logic by using Self-Healing Cells
作者： Thomas Panhofer , Werner Friesenbichler , Martin Delvai
DOI: 10.1109/ICCD.2008.4751832
关键词:
摘要: The trend towards higher integration and faster operating speed leads to decreasing feature sizes lower supply voltages in modern integrated circuits. These properties make the circuits more error-prone, requiring a fault tolerant implementation for applications demanding high reliability, e.g. space missions. In previous work we presented concept how obtain digital by using asynchronous four-state logic (FSL). This type of already exhibits degree tolerance where most faults simply halt circuit (deadlock). remaining types are handled temporal redundancy. Adding deadlock detection unit introducing self-healing cells (SHCs) highly reliable that is able tolerate even multiple faults. However our experiments revealed some specific constellations neither cause nor they detected redundant calculation. We present two improved ways error detection, which allow capture these Further, comparison between size an SHC achieved wrt. performed.
tudelft.nl 参考文章(14)
S.J. Piestrak, T. Nanya, Towards totally self-checking delay-insensitive systems ieee international symposium on fault tolerant computing. pp. 228- 237 ,(1995) , 10.1109/FTCS.1995.466975
Wonjin Jang, A. Martin, SEU-tolerant QDI circuits [quasi delay-insensitive asynchronous circuits] ieee international symposium on asynchronous circuits and systems. pp. 156- 165 ,(2005) , 10.1109/ASYNC.2005.30
Stefan Raaijmakers, Stephan Wong, Run-Time Partial Reconfiguration for Removal, Placement and Routing on the Virtex-II Pro field-programmable logic and applications. pp. 679- 683 ,(2007) , 10.1109/FPL.2007.4380744
Steven A. Guccione, Delon Levi, XBI: a Java-based interface to FPGA hardware Configurable Computing: Technology and Applications. ,vol. 3526, pp. 97- 102 ,(1998) , 10.1117/12.327023
A.J. McAuley, Four state asynchronous architectures IEEE Transactions on Computers. ,vol. 41, pp. 129- 142 ,(1992) , 10.1109/12.123391
Y. Monnet, M. Renaudin, R. Leveugle, Hardening techniques against transient faults for asynchronous circuits international on line testing symposium. pp. 129- 134 ,(2005) , 10.1109/IOLTS.2005.30
O.A. Petlin, S.B. Furber, Built-in self-testing of micropipelines international symposium on advanced research in asynchronous circuits and systems. pp. 22- 29 ,(1997) , 10.1109/ASYNC.1997.587142
C. LaFrieda, R. Manohar, Fault detection and isolation techniques for quasi delay-insensitive circuits dependable systems and networks. pp. 41- 50 ,(2004) , 10.1109/DSN.2004.1311875
Edward J. McCluskey, Wei-Je Huang, Column-Based Precompiled Configurating Techniques for FPGA Fault Tolerance field programmable custom computing machines. ,(2001)
Song Peng, R. Manohar, Fault tolerant asynchronous adder through dynamic self-reconfiguration international conference on computer design. pp. 171- 179 ,(2005) , 10.1109/ICCD.2005.56