Circuit for high-resolution phase detection in a digital RF processor

摘要: A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within digital radio processor. The TDC core is based on pseudo-differential architecture making it insensitive to NMOS PMOS transistor mismatches. time conversion resolution equal inverter propagation delay, e.g., 20 ps, which the finest logic-level regenerative timing CMOS. self calibrating with estimation accuracy better than 1%. circuit can also serve CMOS process strength estimator for analog circuits large SoC dies. employs power management circuitry reduce consumption very low level.