作者: John G. Bartkowiak , Safdar M. Asghar
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摘要: The communications processor of the present invention comprises, in a single integrated circuit chip, combination central processing unit (CPU) having an execution with arithmetic logic and accumulators, program counter, memory, clock generator, timer, bus interface, chip select outputs, interrupt processor; digital signal (DSP) instruction set to carry out algorithm, for carrying multiply accumulate operations external interface; address connected between CPU DSP; data static scheduler statically scheduling algorithm CPU.