Design and Analysis of an Approximate Adder with Hybrid Error Reduction

摘要: This paper presents an energy-efficient approximate adder with a novel hybrid error reduction scheme to significantly improve the computation accuracy at cost of extremely low additional power and area overheads. The proposed utilizes only two input bits adjusts outputs reduce distance, which leads overall improvement in accuracy. design, when implemented 65-nm CMOS technology, has 3, 2, 2 times greater energy, power, efficiencies, respectively, than conventional accurate adders. In terms accuracy, allows that rate decreases 50% whereas those lower-part OR optimized constant reach 68% 85%, respectively. Furthermore, up 2.24, 1.16 better performance respect mean normalized distance (NMED), relative other considered this paper. Importantly, because excellent design tradeoff among delay, is found be most competitive jointly analyzed hardware Specifically, our achieves 51%, 49%, 47% reductions power-, energy-, error-delay-product-NMED products, compared