作者： N.P. van der Meijs , F. Beeftink , A.J. van Genderen , P.J.H. Elias
DOI:
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摘要: can be simulated while fully taking into account allparasitic elements. This is important, since the decrease of feature sizes and increaseof chip dimensions make influence wiring parasitics on performance thechip critical, or even dominant: Gate delays but may actuallyincrease.Since