作者: A.F. Tenca , M.D. Ercegovac
DOI: 10.1109/ARITH.1999.762827
关键词:
摘要: We present a design of high-radix on-line division suitable for long precision computations. The proposed scheme uses quotient-digit selection function based on the residual rounding and scaling operands. bounds number cycles cycle time radix 2/sup k/ n-bit are obtained in terms full-adder delays. speedup with respect to 2 is greater than 3.3 k/spl ges/6 n/spl ges/64. cost increases as radix. For case r=64 n=64, increase area r=2 about 6.6 times plus 512/spl times/10-bit table. has been designed verified using VHDL 1.2 /spl mu/m CMOS standard gate technology from MOSIS library.