Custom purpose regular expression processor architecture for network processing

作者: Sakir Sezer , Dwayne Burns

DOI: 10.1109/ISCAS.2012.6271507

关键词:

摘要: In this paper we introduce the architecture and system platform of a new regular expression processor for next generation security platforms content awareness network processing. The first outlines feature requirements state-of-the-art systems, then presents proposed processing architecture.

参考文章(6)
Vern Paxson, Bro: a system for detecting network intruders in real-time Computer Networks. ,vol. 31, pp. 2435- 2463 ,(1999) , 10.1016/S1389-1286(99)00112-7
Fang Yu, R.H. Katz, T.V. Lakshman, Gigabit rate packet pattern-matching using TCAM international conference on network protocols. pp. 174- 183 ,(2004) , 10.1109/ICNP.2004.1348108
R. Sidhu, V.K. Prasanna, Fast Regular Expression Matching Using FPGAs field-programmable custom computing machines. pp. 227- 238 ,(2001) , 10.1109/FCCM.2001.22
Maya Gokhale, Dave Dubois, Andy Dubois, Mike Boorman, Steve Poole, Vic Hogsett, Granidt: Towards Gigabit Rate Network Intrusion Detection Technology field programmable logic and applications. pp. 404- 413 ,(2002) , 10.1007/3-540-46117-5_43
Abhishek Mitra, Walid Najjar, Laxmi Bhuyan, Compiling PCRE to FPGA for accelerating SNORT IDS Proceedings of the 3rd ACM/IEEE Symposium on Architecture for networking and communications systems - ANCS '07. pp. 127- 136 ,(2007) , 10.1145/1323548.1323571
B.L. Hutchings, R. Franklin, D. Carver, Assisting network intrusion detection with reconfigurable hardware field-programmable custom computing machines. pp. 111- 120 ,(2002) , 10.1109/FPGA.2002.1106666