Method and apparatus for precisely identifying effective addresses associated with hardware events

摘要: A system and method for precisely identifying an instruction causing a performance-related event is disclosed. The may be detected while in pipeline stage of microprocessor preceding writeback the microprocessor's architectural state not updated until after information captured. flushed from pipeline, along with other instructions same thread. hardware trap taken when and/or counter overflows or within given range overflowing. software handler capture log instruction, such as one more extended address elements, before returning control initiating retry instruction. captured logged stored space database usable by data profiler to identify performance bottlenecks application containing