Floating-point multiply-add-fused with reduced latency
作者： T. Lang , J.D. Bruguera
DOI: 10.1109/TC.2004.44
关键词:
摘要: We propose architecture for the computation of double-precision floating-point multiply-add-fused (MAP) operation A + (B /spl times/ C). This is based on combined addition and rounding (using a dual adder) in anticipation normalization step before addition. Because performed addition, it not possible to overlap leading-zero-anticipator with adder. Consequently, avoid increase delay, we modify design LZA so that leading bits its output are produced first can be used begin normalization. Moreover, parts also anticipated. have estimated delay resulting considering load introduced by long connections, estimate reduction between 15 percent 20 percent, respect previous implementations.
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