Exploiting Single-Usage for Effective Memory Management

摘要: Efficient memory management is crucial when designing high performance processors. Upon a miss, the conventional operation mode of cache hierarchy to retrieve missing block from lower levels and store it into all levels. It however difficult assert that storing intermediate will be really useful. In particular, this unnecessary if accessed only once before getting evicted - i.e. single-usage block. This paper typically concerned with reducing number blocks. Our observations reveal blocks are significant at runtime especially in lowest level. We show using an address-based prediction mechanism sufficient identify phenomenon. Two schemes examined remove pollution caused by blocks: bypass scheme replacement policy. results leveraging beneficial memory-intensive applications running on superscalar multi-core architectures.