On the Scalability and Dynamic Load-Balancing of Time Warp

摘要: As a consequence of Moore’s law, the size of in-tegrated circuits has grown extensively, resulting in simulation becoming the major bottleneck in the circuit design process. On the other hand, parallel or distributed simulations can be applied as fast, feasible and cost effective approaches for correctness analysis of current VLSI circuits. In this paper, we developed the first Time Warp simulator which can simulate in parallel all synthesizable Verilog circuits. We observed 4,000,000 events per second on 32 processors for the Viterbi decoder with 800k gates. We also observed that the load of different processors differ by up to 12M events during the course of the simulation. As a result, we first develop two new dynamic load balancing approach which balance the load during the simulation. Afterward, we utilize reinforcement learning to create an algorithm which is a combination of the first two algorithms. We investigate the algorithms on gate level simulations of several open source VLSI circuits. Our results show up to a 25% improvement in the simulation time using the reinforcement learning algorithm. To the best of our knowledge, this is the first time that reinforcement learning has been used for the dynamic load-balancing of Time Warp.