On the suitability of SHA-3 finalists for lightweight applications

摘要: In this study, we investigate the suitability of SHA-3 finalists for lightweight applications. For each finalist, we try to achieve the lowest reported gate count while maintaining a respectable throughput. Our approach differs from all previous SHA-3 implementations, which mainly focus on high performance in terms of throughput. We mainly favor a word-serial approach in our designs to achieve low gate count, where the word size varies from 8 to 64-bits depending on the structure of the hash function and the tradeoff between throughput and area. All hash function cores are realized in Verilog-HDL, synthesized using 90nm UMC CMOS standard cell library and optimized for area for prototyping. A generic FIFO based I/O interface is also built in order to establish data transfer between an external controller and the active hash function core. Results show that, Grøstl has the lowest gate count, while BLAKE gives the best throughput and throughput/area figures. To the best of our knowledge, this is the first comprehensive study on the suitability of SHA-3 finalists for lightweight applications.