Benchmarking ConCISe

摘要: Philips ConCISe architecture proposes a simple, yet cost-effective approach to Reconfigurable Computing, which is expected to penetrate the embedded processors market. ConCISe’s Reconfigurable Function Unit (RFU) approach improves the efficiency of a standard processor for applications biased towards bit manipulations (eg cryptography, networking) by adding dinamically reconfigurable, application specific operations to the processor’s instruction set. In order to get insight into the’performance vs cost’trade-offs that the technique represents, a cycle-based simulator for ConCISe was developed. This report gives account of the simulation-based benchmark results carried out, and makes a cost/performance comparision between silicon real-state investments in an RFU and in bigger caches, to improve processor performance.Conclusions: The functional correctness of the ConCISe approach was ensured. Also, benchmark results show that the RFU allows for a speedup, ignoring run-time effects, ranging from nearly 8%(MD5 algorithm) up to more than 60%(DES crypto algorithm). Cache behaviour has been shown to have a considerable influence on the speed-up delivered by ConCISe’s RFU, as speed-up is reduced by large amounts of data cache misses. Therefore, ConCISe is better off with data caches large enough. On the other hand, the RFU has the side-effect of improving instruction cache performance, c© Philips Electronics NV 1999 iii