Dependence of the post-breakdown performance of MOS devices on the gate oxide BD spot electrical properties

摘要: Dielectric breakdown (BD) of the gate oxide (SiO2) is a crucial issue in the reliability of MOS devices. Nowadays, it is accepted that the oxide failure is an extremely local phenomenon, which takes place in a region several orders of magnitude smaller than the total oxide area (the area of the percolation path has been estimated to be of the order of S0~ 10-13-10-12 cm2 [1]). However, nanoscale experiments reveal that the region affected by the BD can be much larger. Transmission Electron Microscopy [2, 3], which allows to study the BD structural damage, shows that although sometimes the affected region can be comparable to the percolation path area, S0, it can be as large as~ 104 nm2. On the other hand, Conductive Atomic Force Microscopy (C-AFM) has demonstrated that the region electrically affected (SBD) by the BD event can have a size of~ 300nm [4]. Since this area could be as large as the MOSFET gate size, the post-BD device performance would not have to depend on the position of the BD event along the channel. The aim of this work is to clarify this point. With this purpose, macroscopic tests (on MOS transistors) will be combined with C-AFM experiments to determine the influence of the BD spot electrical properties on the post-BD conduction of MOS devices. Fig. 1 shows a typical C-AFM current image of the gate area of an MOS structure (tox= 3.5 nm) that was previously stressed until BD with a ramped voltage stress. After the stress, the polysilicon gate was removed with a very selective etching to allow the scanning of the structure with the tip of the C-AFM. The image shows a brighter region (larger currents), which has been …