Timothy (Tod) Dickson
机构: Principal Research Scientist, IBM T.J. Watson Research Center
每年引用次数
引用次数
引用: 2,816
H-指数: 29
I10-指数 : 46
出版物: 85
High-Speed SiGeBiCMOSTechnologies: 120-nmStatus andEnd-of-Roadmap Challenges
G. Dambrine , N. Zerounian , L. Rubaldo , D. Dutartre
42
2007
A 2-GHz Direct Sampling Delta-Sigma Tunable Receiver with 40-GHz Sampling Clock and on-chip PLL
T. Chalvatzis , T. O. Dickson , S. P. Voinigescu
symposium on vlsi circuits 54 -55
5
2007
A 32 Gb/s, 4.7 pJ/bit optical link with- 11.7 dBm sensitivity in 14-nm FinFET CMOS
Jonathan E Proesel , Zeynep Toprak-Deniz , Alessandro Cevrero , Ilter Ozkaya
IEEE Journal of Solid-State Circuits 53 ( 4) 1214 -1226
59
2017
A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links
Timothy O Dickson , Zeynep Toprak Deniz , Martin Cochet , Troy J Beukema
IEEE Journal of Solid-State Circuits 58 ( 4) 1074 -1086
2
2022
4-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phases
Timothy O Dickson , KIM Bongjin
28
2019
Sampled current-integrating decision feedback equalizer and method
John F Bulzacchelli , Timothy O Dickson , Daniel J Friedman , Alexander V Rylyakov
17
2011
Power-scalable skew compensation in source-synchronous parallel interfaces
Ankur Agrawal , Timothy O Dickson , Sergey Rylov
1
2016
Timing recovery method and apparatus for an input/output bus with link redundancy
John F Bulzacchelli , Timothy O Dickson , Daniel J Friedman , Yong Liu
1
2014
ISSCC 2009/SESSION 21/10Gb/s-TO-40Gb/s TRANSMITTERS AND RECEIVERS/21.6
John F Bulzacchelli , Timothy O Dickson , Zeynep Toprak Deniz , Herschel A Ainspan
A 128-Gb/s 1.3-pJ/b PAM-4 transmitter with reconfigurable 3-tap FFE in 14-nm CMOS
Zeynep Toprak-Deniz , Jonathan E Proesel , John F Bulzacchelli , Herschel A Ainspan
IEEE Journal of Solid-State Circuits 55 ( 1) 19 -26
61
2019
Transmitter with uniform driver segment activity
Timothy O Dickson , Martin Cochet , Zeynep Toprak-Deniz , John Francis Bulzacchelli
2023
Serial transmitter with feed forward equalizer and timing calibration
Timothy O Dickson , Mounir Meghelli
11
2018
Serial transmitter with feed forward equalizer
Timothy O Dickson , Mounir Meghelli
3
2018
Serial transmitter with feed forward equalizer
Timothy O Dickson , Mounir Meghelli
1
2019
ISSCC 2009/SESSION 10/MULTI-Gb/s SERIAL LINKS AND BUILDING BLOCKS/10.2
Yong Liu , Byungsub Kim , Timothy O Dickson , John F Bulzacchelli
Dual duty cycle correction loop for a serializer/deserializer (SerDes) transmitter output
Jieming Qi , Daniel Mark Dreps , Glen A Wiedemeier , Eric John Lukes
2023
Efficient calibration of a low power parallel data communications channel
Timothy O Dickson , Daniel M Dreps , Frank D Ferraiolo , Douglas J Joseph
2017
Efficient calibration of a low power parallel data communications channel
Timothy O Dickson , Daniel M Dreps , Frank D Ferraiolo , Douglas J Joseph
2016
Fault tolerant parallel receiver interface with receiver redundancy
Timothy O Dickson , Daniel M Dreps , Frank D Ferraiolo
2014
“A 10-Gb/s Compact Low-Power Serial I/O with DFE-IIR Equalization in 65-nm CMOS,” Deemed Best 2009 JSSC Paper
John F Bulzacchelli Friedman , Timothy O Dickson , Yong Liu , Byungsub Kim
IEEE Solid-State Circuits Magazine 55 -55
2011