ISSCC 2009/SESSION 10/MULTI-Gb/s SERIAL LINKS AND BUILDING BLOCKS/10.2

摘要: The design of compact low-power I/O transceivers continues to be a challenge for both chip-to-chip and backplane applications. The introduction of dense fine-pitch silicon packaging technologies, that in principle are capable of supporting tens of thousands of high-data-rate I/O for local chip-to-chip interconnect, will make I/O area and power requirements even more stringent. Figure 10.2. 1 depicts two chips mounted on a silicon (Si) carrier [1], an example of such a dense packaging technology, and connected by fine-pitch interconnects. Characteristics of an example 20mm Si carrier channel are shown in Fig. 10.2. 1, showing significant (~ 6dB) DC attenuation as well as 17dB of loss at 5GHz. In the time domain, the response to an isolated ‘1’applied at 10Gb/s shows many postcursors. A DFE would require many taps to be effective, however, the power and area penalty would be prohibitive in this context. This …