Placement of 3D ICs with Thermal and Interlayer Via Considerations

Sapatnekar , Goplen
design automation conference 626 -631

2007
GLARE: Global and local wiring aware routability evaluation

Wei , Sapatnekar , Reddy , Tellez
design automation conference 768 -773

2012
A framework for block-based timing sensitivity analysis

Kashyap , Kumar , Sapatnekar
design automation conference 688 -693

17
2008
NBTI-Aware Synthesis of Digital Circuits

Kim , Kumar , Sapatnekar
design automation conference 370 -375

275
2007
Reinventing EDA with manycore processors

Meier , Keutzer , Kirkpatrick , Spyrou
design automation conference 126 -127

2008
A method for correcting the functionality of a wire-pipelined circuit

Nookala , Sapatnekar
design automation conference 570 -575

2004
A predictive distributed congestion metric and its application to technology mapping

Rupesh S. Shelar , Sachin S. Sachin S. Sapatnekar , Prashant Saxena , Xinning Wang
international symposium on physical design 210 -217

8
2004
Minimum area retiming with equivalent initial states

Maheshwari , Sapatnekar
international conference on computer aided design 216 -219

8
1997
Enabling improved power management in multicore processors through clustered DVFS

T Kolpe , A Zhai , S S Sapatnekar
design, automation, and test in europe 293 -298

74
2011
A Comparative Study Between Spin-Transfer-Torque and Spin-Hall-Effect Switching Mechanisms in PMTJ Using SPICE

Ibrahim Ahmed , Zhengyang Zhao , Meghna G. Mankalale , SACHIN S. Sapatnekar
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 3 74 -82

45
2017
IEEE Awards

Giovanni De Micheli , John Maxwell Cohn , Rolf Ernst , Andreas Kuehlmann

A convex programming approach to problems in VLSI design

Sachin Suresh Sapatnekar
University of Illinois at Urbana-Champaign

13
1992
Parallel Algorithms for Layout Compaction on the Connection Machine

Sachin Suresh Sapatnekar
Syracuse University

1989
Editor-at-Large board

ALBERTO SANGIOVANNI VINCENTELLI , YERVANT ZORIAN , ROBA RUTENBAR , SACHIN S SAPATNEKAR

A Convex Programming Approach for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers

Shankar Ramaswamyy , Sachin Sapatnekarz , Prithviraj Banerjeey
To appear in the Proceedings of the International Conference on Parallel Processing 94 1 -1

6
A Framework for Exploiting Data and Functional Parallelism on Distributed Memory Multicomputers

Shankar Ramaswamyy , Sachin Sapatnekarz , Prithviraj Banerjeey

Clustering based pruning for statistical criticality computation under process variations

Hushrav D Mogal , Haifeng Qian , Kia Bazargan , Sachin S Sapatnekar
international conference on computer aided design 340 -343

17
2007
Tutorial: High-speed interconnect technology: On-chip and off-chip

Ramesh Harjani , Sachin S Sapatnekar , Jaijeet Roychowdhury
international conference on vlsi design

2005
Filtered Audio Clips from Approximate FIR Filters Designed Using the SABER Algorithm

Deepashree Sengupta , Farhana Snigdha , Jiang Hu , Sachin S Sapatnekar

2017
Computer-aided design of 3d integrated circuits

Sachin S Sapatnekar
Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07 317 -317

2007