Jiang Hu
机构: Professor of Electrical and Computer Engineering, Texas A&M University
主页: tamu.edu
每年引用次数
引用次数
引用: 6,333
H-指数: 46
I10-指数 : 128
出版物: 267
Ocin_tsim: a DVFS-aware simulator for NoC based platforms.
Boris Grot , J Hu , P.V. Gratz , S Prabhu
11
2009
Efficient Congestion Mitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies
Chaudhry MAR , Z Asad , A Sprintson , J Hu
VLSI Design 2011
(294) Trends and Clinical Practice Patterns of Prostatic Urethral Lift (PUL): An Analysis of the American Board of Urology Case Logs
S Thorogood , T Zhang , C Sze , M Strasser
The Journal of Sexual Medicine 20 ( Supplement_1) qdad060. 275 -qdad060. 275
2023
Analog IP Protection and Evaluation
NG Jayasankaran , A Sanabria-Borbón , E Sánchez-Sinencio , J Hu
Springer International Publishing 419 -469
2020
7A. 4 Practical Techniques for Minimizing Skew and Its Variation in Buffered Clock Networks
G Venkataraman , N Jayakumar , J Hu , P Li
IEEE ACM INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN 2005 592 -592
2005
Layer assignment for crosstalk risk minimization
Jiang Hu , Di Wu , Min Zhao , Rabi Mahapatra
asia and south pacific design automation conference 159 -162
18
2004
Modeling, optimization and control of rotary traveling-wave oscillator
Cheng Zhuo , Rupak Samanta , Jiang Hu , Kangsheng Chen
international conference on computer aided design 476 -480
19
2007
Physical design techniques for optimizing RTA-induced variations
Sachin S. Sapatnekar , Yaoguang Wei , Frank Liu , Jiang Hu
asia and south pacific design automation conference 745 -750
5
2010
Timing verification for adaptive integrated circuits
Ulf Schlichtmann , Yiren Shen , Jiang Hu , Bing Li
design, automation, and test in europe 1587 -1590
8
2015
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Yanfeng Wang , Yici Cai , Qiang Zhou , Jiang Hu
asia and south pacific design automation conference 370 -375
3
2008
DiCER: distributed and cost-effective redundancy for variation tolerance
Jiang Hu , Quiyang Li , Di Wu , G. Venkataraman
international conference on computer aided design 393 -397
3
2005
Handling partial correlations in yield prediction
Janet Wang , Jiang Hu , Sridhar Varadan
asia and south pacific design automation conference 543 -548
2008
Unified adaptivity optimization of clock and logic signals
Shiyan Hu , Jiang Hu
international conference on computer aided design 125 -130
16
2007
SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal
Yici Cai , Qiang Zhou , Jiang Hu , Fan Yang
design, automation, and test in europe 1369 -1372
7
2010
A place and route aware buffered Steiner tree construction
CN Sze , Jiang Hu , Charles J Alpert ,
asia and south pacific design automation conference 355 -360
6
2004
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding
Rajendran Panda , Xiaoji Ye , Jiang Hu , Min Zhao
international conference on computer aided design 627 -631
19
2007
Buffer Insertion Basics.
Shiyan Hu , Zhuo Li , Jiang Hu
Handbook of Algorithms for Physical Design Automation
2008
Buffering in the Layout Environment.
Jiang Hu , Cliff C. N. Sze
Handbook of Algorithms for Physical Design Automation
2008
Filtered Audio Clips from Approximate FIR Filters Designed Using the SABER Algorithm
Deepashree Sengupta , Farhana Snigdha , Jiang Hu , Sachin S Sapatnekar
2017