Chuck Alpert
机构: Fellow, Cadence Design Systems
每年引用次数
引用次数
引用: 10,830
H-指数: 51
I10-指数 : 145
出版物: 311
GLARE: Global and local wiring aware routability evaluation
Wei , Sapatnekar , Reddy , Tellez
design automation conference 768 -773
2012
Placement: Hot or Not?
Ward , Li , Viswanathan , Nam
international conference on computer aided design 283 -290
2012
A direct combination of the Prim and Dijkstra constructions for improved performance-driven global routing
C.J. Alpert , T.C. Hu , J.H. Huang , A.B. Kahng
1993 IEEE International Symposium on Circuits and Systems 1869 -1872
57
1993
Minimum density interconnection trees
C.J. Alpert , J. Cong , A.B. Kahng , G. Robins
1993 IEEE International Symposium on Circuits and Systems 1865 -1868
1
1993
A general framework for vertex orderings with applications to circuit clustering
C.J. Alpert , A.B. Kahng
IEEE Transactions on Very Large Scale Integration Systems 4 ( 2) 240 -246
17
1996
Buffer library selection
C.J. Alpert , R.G. Gandham , J.L. Neves , S.T. Quay
international conference on computer design 221 -226
20
2000
Hypergraph partitioning with fixed vertices [VLSI CAD]
C.J. Alpert , A.E. Caldwell , A.B. Kahng , I.L. Markov
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 19 ( 2) 267 -272
20
2000
Interconnect synthesis without wire tapering
C.J. Alpert , A. Devgan , J.P. Fishburn , S.T. Quay
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20 ( 1) 90 -104
41
2001
Steiner tree optimization for buffers, blockages, and bays
C.J. Alpert , G. Gandham , Jiang Hu , J.I. Neves
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20 ( 4) 556 -562
39
2001
RC delay metrics for performance optimization
C.J. Alpert , A. Devgan , C.V. Kashyap
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 20 ( 5) 571 -582
126
2001
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design
C.J. Alpert , T.C. Hu , J.H. Huang , A.B. Kahng
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 14 ( 7) 890 -896
80
1995
Multiway partitioning via geometric embeddings, orderings, and dynamic programming
C.J. Alpert , A.B. Kahng
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 14 ( 11) 1342 -1358
53
1995
A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment
Shiyan Hu , Zhuo Li , C.J. Alpert
IEEE Transactions on Circuits and Systems Ii-express Briefs 56 ( 7) 580 -584
8
2009
Simple eigenvector-based circuit clustering can be effective [VLSI CAD]
C.J. Alpert , A.B. Kahng
international symposium on circuits and systems 4 683 -686
1996
A clock distribution network for microprocessors
P.J. Restle , T.G. McNamara , D.A. Webber , P.J. Camporese
IEEE Journal of Solid-state Circuits 36 ( 5) 792 -799
373
2001
A hybrid multilevel/genetic approach for circuit partitioning
C.J. Alpert , L.W. Hagen , A.B. Kahng
asia pacific conference on circuits and systems 298 -301
61
1996
Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees
C.V. Kashyap , C.J. Alpert , F. Liu , A. Devgan
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23 ( 4) 509 -516
56
2004
Correction to "Interconnect synthesis without wire tapering"
C.J. Alpert , A. Devgan , J.P. Fishburn , S.T. Quay
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 21 ( 4) 497 -497
1
2002
Minimum buffered routing with bounded capacitive load for slew rate and reliability control
C.J. Alpert , A.B. Kahng , Bao Liu , I.I. Mandoiu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22 ( 3) 241 -253
20
2003
Effective free space management for cut-based placement via analytical constraint generation
C.J. Alpert , Gi-Joon Nam , P.G. Villarrubia
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22 ( 10) 1343 -1353
22
2003