引用次数
引用: 2,593
H-指数: 27
I10-指数 : 59
出版物: 184
On improved graph-based alternative wiring scheme for multi-level logic optimization
Y.-L. Wu , C.-N. Sze , C.-C. Cheung , H. Fan
international conference on electronics circuits and systems 2 654 -657
8
2000
Integrated Placement and Skew Optimization for Rotary Clocking
G. Venkataraman , Jiang Hu , F. Liu , C-N. Sze
design, automation, and test in europe 1 756 -761
25
2006
LEADING-EDGE COMPUTER AIDED DESIGN SOLUTIONS FOR ADVANCED DIGITAL AND MIXED-SIGNAL SYSTEMS-ON-CHIPS
A Sangiovanni-Vincentelli , D Sylvester , A Srivastava , K Bard
Proceedings of the IEEE 95 ( 3)
2007
Timing-driven Steiner trees are (practically) free
Charles J Alpert , Andrew B Kahng , CN Sze , Qinke Wang
design automation conference 389 -392
29
2006
Making fast buffer insertion even faster via approximation techniques
Zhuo Li , CN Sze , Charles J Alpert , Jiang Hu
asia and south pacific design automation conference 1 13 -18
28
2005
A place and route aware buffered Steiner tree construction
CN Sze , Jiang Hu , Charles J Alpert ,
asia and south pacific design automation conference 355 -360
6
2004
Clocking and the ISPD’09 clock synthesis contest
CN Sze , P Restle , GJ Nam , CJ Alpert
Proc. ISPD 149 -150
21
2009
Grid to Ports Clock Routing for Ports Clock Routing for Grid-to-Ports Clock Routing for Ports Clock Routing for High Performance Microprocessor Designs
Haitong Tian , Wai-Chung Tang , Evangeline FY Young , CN Sze
2011
SPECIAL ISSUE-LEADING-EDGE COMPUTER AIDED DESIGN SOLUTIONS FOR ADVANCED DIGITAL AND MIXED-SIGNAL SYSTEMS-ON-CHIPS-Techniques for Fast Physical Synthesis
CJ Alpert , SK Karandikar , Z Li , GJ Nam
Proceedings of the IEEE 95 ( 3) 573 -573
2007
Occlusion-resistant locomotion analysis of piglets using amodal instance segmentation
H Gan , A Mao , CN Sze , E Huang
2nd US Precision Livestock Farming Conference 78 -84
2023
Baosheng Wang Barbara Jobstmann Bart Vermeulen Bashir M. Al-Hashimi
Ben Gu , Amandeep Singh , Amit Patra , Amith Singhee
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 30 ( 1) 2 -2
2011
Techniques for Fast Physical Synthesis
Charles J Alpert , Shrirang K Karandikar , Zhuo Li , Gi-Joon Nam
Proceedings of the IEEE 95 ( 3) 573 -599
70
2007
Ispd2009 clock network synthesis contest
Cliff N Sze , Phillip Restle , Gi-Joon Nam , Charles Alpert
Proceedings of the 2009 international symposium on Physical design - ISPD '09 149 -150
50
2009
Quantifying academic placer performance on custom designs
Samuel I Ward , David A Papa , Zhuo Li , Cliff N Sze
Proceedings of the 2011 international symposium on Physical design - ISPD '11 91 -98
18
2011
Obstacle-avoiding and slew-constrained clock tree synthesis with efficient buffer insertion
Yici Cai , Chao Deng , Qiang Zhou , Hailong Yao
IEEE Transactions on very large scale Integration (VLSI) Systems 23 ( 1) 142 -155
29
2014
Hardware acceleration of an efficient and accurate proton therapy Monte Carlo
Thomas H Osiecki , Min-yu Tsai , Anne E Gattiker , Damir A Jamsek
Procedia Computer Science 18 2241 -2250
6
2013
Research Experience
CLIFF SZE
Cell 1 ( 979) 739 -4144
2010
CATALYST: planning layer directives for effective design closure
Yaoguang Wei , Zhuo Li , Cliff Sze , Shiyan Hu
design, automation, and test in europe 1873 -1878
9
2013
The ISPD global routing benchmark suite
Gi-Joon Nam , Cliff Sze , Mehmet Yildiz
international symposium on physical design 156 -159
43
2008
The ISPD-2011 routability-driven placement contest and benchmark suite
Natarajan Viswanathan , Charles J Alpert , Cliff Sze , Zhuo Li
Proceedings of the 2011 international symposium on Physical design - ISPD '11 141 -146
94
2011