A place and route aware buffered Steiner tree construction

摘要: In order to achieve timing closure on increasingly complex IC designs, buffer insertion needs be performed thousands of nets within an integrated physical synthesis system. most previous works, buffers may inserted at any open space. Even when there appear space for in the alleys between large blocks, these regions are often densely packed or useful later fix critical paths. addition, a solution inadvertently force wires go through routing congested regions. Therefore, synthesis, scheme aware both placement congestion and existing layout so it has able decide insert dense performance improvement utilize sparser chip. With proposed Steiner tree adjustment technique, this work aims finding congestion-aware buffered trees. Our technique takes as input, modifies simultaneously handles objectives timing, congestion. To our knowledge, is first study, which considers three problem. Experimental results confirm effectiveness algorithm while achieves up 20x speed-up comparing with state-of-the-art (C.J. Alpert et al., 2003).