引用次数
引用: 2,593
H-指数: 27
I10-指数 : 59
出版物: 184
Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization
Feifei Niu , Qiang Zhou , Hailong Yao , Yici Cai
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '11 199 -204
9
2011
Wire synthesizable global routing for timing closure
Michael D. Moffitt , C. N. Sze
16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011) 545 -550
3
2011
Performance-driven multi-level clustering for combinational circuits
C. N. Sze , Ting-Chi Wang
asia and south pacific design automation conference 729 -740
3
2003
Register placement for low power clock network
Yongqiang Lu , C. N. Sze , Xianlong Hong , Qiang Zhou
asia and south pacific design automation conference 1 588 -593
11
2005
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results
C. N. Sze
international symposium on physical design 143 -143
62
2010
Navigating registers in placement for clock network minimization
Yongqiang Lu , C. N. Sze , Xianlong Hong , Qiang Zhou
design automation conference 176 -181
44
2005
Postgrid Clock Routing for High Performance Microprocessor Designs
Haitong Tian , Wai-Chung Tang , Evangeline F. Y. Young , C. N. Sze
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 31 ( 2) 255 -259
2012
Grid-to-ports clock routing for high performance microprocessor designs
Haitong Tian , Wai-Chung Tang , Evangeline F.Y. Young , C.N. Sze
Proceedings of the 2011 international symposium on Physical design - ISPD '11 21 -28
3
2011
An optimized routing scheme and a channel reservation strategy for a low Earth orbit satellite system
P.T.S. Tam , J.C.S. Lui , H.W. Chan , C.C.N. Sze
vehicular technology conference 5 2870 -2874
4
1999
Optimal circuit clustering with variable interconnect delay
C.N. Sze , Ting-Chi Wang
international symposium on circuits and systems 4 707 -710
1
2002
Optimal circuit clustering for delay minimization under a more general delay model
C.N. Sze , Ting-Chi Wang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 22 ( 5) 646 -651
5
2003
Multilevel circuit clustering for delay minimization
C.N. Sze , T.-C. Wang , L.-C. Wang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23 ( 7) 1073 -1085
13
2004
Accurate estimation of global buffer delay within a floorplan
C.J. Alpert , Jiang Hu , S.S. Sapatnekar , C.N. Sze
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25 ( 6) 1140 -1145
33
2006
Buffering in the Layout Environment.
Jiang Hu , Cliff C. N. Sze
Handbook of Algorithms for Physical Design Automation
2008
Gate sizing and threshold voltage assignment for high performance microprocessor designs
Tiago Reimann , Cliff C. N. Sze , Ricardo Reis
asia and south pacific design automation conference 214 -219
6
2015
Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration
Johann Knechtel , Ozgur Sinanoglu , Ibrahim (Abe) M. Elfadel , Jens Lienig
Ipsj Transactions on System Lsi Design Methodology 10 45 -62
41
2017