Gate sizing and threshold voltage assignment for high performance microprocessor designs

摘要: Timing-constrained power-driven gate sizing has aroused lot of research interest after the recent two discrete contests organized by International Symposium on Physical Design. Since then, there are plenty papers published and new algorithms proposed based ISPD 2013 contest formulation. However, almost all (new old) in literature ignore details how fits industrial physical synthesis flows, which limits their practical usage. This paper aims at filling this knowledge gap. We explain our approach to integrate a state-of-the-art Lagrangian Relaxation-based into actual framework, challenges issues we observed from point view VLSI design flows.