Techniques for Fast Physical Synthesis

摘要: The traditional purpose of physical synthesis is to perform timing closure , i.e., create a placed design that meets its specifications while also satisfying electrical, routability, and signal integrity constraints. In modern flows, tools hardly ever achieve this goal in their first iteration. team must iterate by studying the output run, then potentially massage input, e.g., changing floorplan, assertions, pin locations, logic structures, etc., order hopefully better solution for next complexity means systems can take days run on designs with multimillions placeable objects, which severely hurts productivity. This paper discusses some newer techniques have been deployed within IBM's tool called PDS significantly improves throughput. particular, we focus biggest contributors runtime, placement, legalization, buffering, electric correction, present generate significant turnaround time improvements