Timing-driven placement using design hierarchy guided constraint generation
作者： Xiaojian Yang , Bo-Kyung Choi , Majid Sarrafzadeh
关键词: Cycles per instruction 、 Electronic circuit 、 Very-large-scale integration 、 Engineering 、 Hierarchy 、 Computer architecture 、 Placement 、 Computer engineering 、 Place and route 、 Integrated circuit layout 、 Cadence
摘要: Design hierarchy plays an important role in timing-driven placement for large circuits. In this paper, we present a new methodology delay budgeting based placement. A novel slack assignment approach is described as well its application on with design information. The proposed flow implemented into tool named Dragon (timing-driven mode), and evaluated using industrial place route flow. Compared to Cadence QPlace, generates results shorter clock cycle better routability.
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