An integrated environment for technology closure of deep-submicron IC designs
作者： L. Trevillyan , D. Kung , R. Puri , L.N. Reddy , M.A. Kazda
关键词:
摘要: With larger chip images and increasingly aggressive technologies, key design processes must interoperate, PDS, a physical-synthesis system, accomplishes technology closure through interacting of logic optimization, placement, timing, clock insertion, routing, all using common infrastructure with robust variable-accuracy analysis abstractions.
ieeecomputersociety.org参考文章(8)
Sabih H. Gerez, Algorithms for VLSI design automation ,(1998)
C.J. Alpert, Gi-Joon Nam, P.G. Villarrubia, Free space management for cut-based placement [IC layout] international conference on computer aided design. pp. 746- 751 ,(2002) , 10.1109/ICCAD.2002.1167615
Charles J Alpert, Anirudh Devgan, Stephen T Quay, None, Buffer insertion with accurate gate and interconnect delay computation design automation conference. pp. 479- 484 ,(1999) , 10.1145/309847.309983
N. Shenoy, M. Iyer, R. Damiano, K. Harer, Hi-Keung Ma, P. Thilking, A robust solution to the timing convergence problem in high-performance design international conference on computer design. pp. 250- 257 ,(1999) , 10.1109/ICCD.1999.808433
J. Vygen, B. Korte, J. Schietke, C. Albrecht, Cycle time and slack optimization for VLSI-chips international conference on computer aided design. pp. 232- 238 ,(1999) , 10.5555/339492.340019
Ruchir Puri, David S. Kung, Anthony D. Drumm, Fast and accurate wire delay estimation for physical synthesis of large ASICs Proceedings of the 12th ACM Great Lakes Symposium on VLSI - GLSVLSI '02. pp. 30- 36 ,(2002) , 10.1145/505306.505314
David Chinnery, Kurt Keutzer, Leon Stok, Ruchir Puri, Subhrajit Bhattacharya, John Cohn, Dennis Sylvester, Ashish Srivastava, Sarvesh Kulkarni, Pushing ASIC performance in a power envelope design automation conference. pp. 788- 793 ,(2003) , 10.1145/775832.776032
Charles J Alpert, Gi-Joon Nam, Paul G Villarrubia, None, Free space management for cut-based placement international conference on computer aided design. pp. 746- 751 ,(2002) , 10.1145/774572.774682