Timing Closure for Multi-Million-Gate Integrated Circuits

作者: David A. Papa , Igor L. Markov

DOI: 10.1007/978-1-4614-1356-1_1

关键词:

摘要: Sophisticated integrated circuits (ICs) can be classified as processors (CPUs), application-specific (ASICs) or systems-on-a-chip (SoCs), which embed CPUs and intellectual property blocks into ASICs. Mass-produced on silicon chips, these fuel consumer industrial electronics, maintain national international computer networks, coordinate transportation power grids, ensure the competitiveness of military systems. The design new requires sophisticated optimization algorithms, software methodologies—collectively called Electronic Design Automation (EDA)—which leverage synergies between Computer Science, Engineering Electrical Engineering.

参考文章(11)
Simone de Beauvoir, The Coming of Age ,(1970)
Charles J Alpert, Anirudh Devgan, Stephen T Quay, None, Buffer insertion with accurate gate and interconnect delay computation design automation conference. pp. 479- 484 ,(1999) , 10.1145/309847.309983
Charles J Alpert, Shrirang K Karandikar, Zhuo Li, Gi-Joon Nam, Stephen T Quay, Haoxing Ren, Cliff N Sze, Paul G Villarrubia, Mehmet C Yildiz, None, Techniques for Fast Physical Synthesis Proceedings of the IEEE. ,vol. 95, pp. 573- 599 ,(2007) , 10.1109/JPROC.2006.890096
P. Saxena, N. Menezes, P. Cocchini, D.A. Kirkpatrick, Repeater scaling and its impact on CAD IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 23, pp. 451- 463 ,(2004) , 10.1109/TCAD.2004.825841
Stephen M. Plaza, Igor L. Markov, Valeria Bertacco, Optimizing non-monotonic interconnect using functional simulation and logic restructuring international symposium on physical design. pp. 95- 102 ,(2008) , 10.1145/1353629.1353653
Charles J. Alpert, Paul G. Villarrubia, Chris Chu, The coming of age of physical synthesis international conference on computer aided design. pp. 246- 249 ,(2007) , 10.5555/1326073.1326124
A. Srinivasan, K. Chaudhary, E.S. Kuh, RITUAL: a performance driven placement algorithm for small cell ICs international conference on computer aided design. pp. 48- 51 ,(1991) , 10.1109/ICCAD.1991.185188
L. Trevillyan, D. Kung, R. Puri, L.N. Reddy, M.A. Kazda, An integrated environment for technology closure of deep-submicron IC designs IEEE Design & Test of Computers. ,vol. 21, pp. 14- 22 ,(2004) , 10.1109/MDT.2004.1261846
L.P.P.P. van Ginneken, Buffer placement in distributed RC-tree networks for minimal Elmore delay international symposium on circuits and systems. pp. 865- 868 ,(1990) , 10.1109/ISCAS.1990.112223
Stephen M. Plaza, Igor L. Markov, Valeria M. Bertacco, Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 27, pp. 2107- 2119 ,(2008) , 10.1109/TCAD.2008.2006156