A novel net weighting algorithm for timing-driven placement

摘要: Net weighting for timing-driven placement has been very popular in industry and academia. It various advantages such as low complexity, high flexibility ease of implementation. Existing net algorithms, however, are often ad-hoc. There is generally no known good algorithms. In this paper, we present a novel algorithm based on the concept path-counting, apply it FPGA application. Theoretically first ever accurate, all-path counting algorithm. Experimental data shows that compared with used state-of-the-art package VPR (A. Marquardt et al, ACM Symp. FPGAs, pp. 203-213, 2000), new can achieve longest path delay reduction up to 38.8%, 15.6% average runtime overhead only 4.1% increase total wirelength.