Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration
作者： Johann Knechtel , Ozgur Sinanoglu , Ibrahim (Abe) M. Elfadel , Jens Lienig , Cliff C. N. Sze
关键词:
摘要: … have been reviewed, eg, by imec’s Eric Beyne in Ref. [23], here along with the related 2D and 3D interconnect … These solutions have also been standardized via IEEE Std 1149.1 [98] …
ai.google 参考文章(113)
Andy Heinig, Robert Fischbach, Enabling automatic system design optimization through Assembly Design Kits ieee international d systems integration conference. ,(2015) , 10.1109/3DIC.2015.7334602
P. Batude, M. Vinet, B. Previtali, C. Tabone, C. Xu, J. Mazurier, O. Weber, F. Andrieu, L. Tosti, L. Brevard, B. Sklenard, P. Coudrain, S. Bobba, H. Ben Jamaa, P-E. Gaillardon, A. Pouydebasque, O. Thomas, C. Le Royer, J.-M. Hartmann, L. Sanchez, L. Baud, V. Carron, L. Clavelier, G. De Micheli, S. Deleonibus, O. Faynot, T. Poiroux, Advances, challenges and opportunities in 3D CMOS sequential integration international electron devices meeting. ,(2011) , 10.1109/IEDM.2011.6131506
Jonathan Valamehr, Mohit Tiwari, Timothy Sherwood, Ryan Kastner, Ted Huffmire, Cynthia Irvine, Timothy Levin, Hardware assistance for trustworthy systems through 3-D integration annual computer security applications conference. pp. 199- 210 ,(2010) , 10.1145/1920261.1920292
Lok-Won Kim, John D. Villasenor, A System-On-Chip Bus Architecture for Thwarting Integrated Circuit Trojan Horses IEEE Transactions on Very Large Scale Integration Systems. ,vol. 19, pp. 1921- 1926 ,(2011) , 10.1109/TVLSI.2010.2060375
Derek K. Shaeffer, MEMS inertial sensors: A tutorial overview IEEE Communications Magazine. ,vol. 51, pp. 100- 109 ,(2013) , 10.1109/MCOM.2013.6495768
Je-Hyoung Park, Ali Shakouri, Sung-Mo Kang, Fast Thermal Analysis of Vertically Integrated Circuits (3-D ICs) Using Power Blurring Method ASME 2009 InterPACK Conference, Volume 2. pp. 701- 707 ,(2009) , 10.1115/INTERPACK2009-89072
Yuan-Kai Ho, Yao-Wen Chang, Multiple chip planning for chip-interposer codesign Proceedings of the 50th Annual Design Automation Conference on - DAC '13. pp. 27- ,(2013) , 10.1145/2463209.2488767
S.L. Wright, R. Polastre, H. Gan, L.P. Buchwalter, R. Horton, P.S. Andry, E. Sprogis, C. Patel, C. Tsang, J. Knickerbocker, J.R. Lloyd, A. Sharma, M.S. Sri-Jayantha, Characterization of micro-bump C4 interconnects for Si-carrier SOP applications electronic components and technology conference. ,(2006) , 10.1109/ECTC.2006.1645716
Jui-Hung Chien, Ruei-Siang Hsu, Hsueh-Ju Lin, Ka-Yi Yeh, Shih-Chieh Chang, Contactless Stacked-die Testing for Pre-bond Interposers design automation conference. pp. 1- 6 ,(2014) , 10.1145/2593069.2593111
Chunbo Zhang, Leijun Li, Characterization and Design of Through-Silicon Via Arrays in Three-Dimensional ICs Based on Thermomechanical Modeling IEEE Transactions on Electron Devices. ,vol. 58, pp. 279- 287 ,(2011) , 10.1109/TED.2010.2089987