Optimal circuit clustering for delay minimization under a more general delay model
作者： C.N. Sze , Ting-Chi Wang
关键词:
摘要: This paper considers the area-constrained clustering of combinational circuits for delay minimization under a more general model, which practically takes variable interconnect into account. Our model is particularly applicable when allowing back-annotation actual information to drive process. We present vertex grouping technique and integrate it with algorithm (Rajaraman Wong, 1995) such that our can be proved solve problem optimally in polynomial time.
sci-hub.se 参考文章(4)
E.L. Lawler, K.N. Levitt, J. Turner, Module Clustering to Minimize Delay in Digital Networks IEEE Transactions on Computers. ,vol. 18, pp. 47- 57 ,(1969) , 10.1109/T-C.1969.222524
H.H. Yang, D.F. Wong, Circuit clustering for delay minimization under area and pin constraints IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 16, pp. 976- 986 ,(1997) , 10.1109/43.658566
R. Murgai, R.K. Brayton, A. Sangiovanni-Vincentelli, On clustering for minimum delay/ara international conference on computer aided design. pp. 6- 9 ,(1991) , 10.1109/ICCAD.1991.185176
R. Rajaraman, D.F. Wong, Optimum clustering for delay minimization IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 14, pp. 1490- 1495 ,(1995) , 10.1109/43.476579