A note on the Complexity of Stockmeyer's floorplan Optimization Technique.

D. F. Wong , Ting-Chi Wang
Algorithmic Aspects of VLSI Layout 309 -320

4
1993
Optimal Redundant Via Insertion Using Mixed Integer Linear Programming

Kuang-Yao Lee , Kai-Yuan Chao , Ting-Chi Wang
Proceedings of VLSI Design/CAD Symposium, Hualien, Taiwan, August 2007 310 -313

1
2007
Simultaneous antenna avoidance and via optimization in layer assignment of multi-layer global routing

Tsung-Hsien Lee , Ting-Chi Wang
international conference on computer aided design 312 -318

16
2010
A resource-level parallel approach for global-routing-based routing congestion estimation and a method to quantify estimation accuracy

Wen-Hao Liu , Zhen-Yu Peng , Ting-Chi Wang
international conference on computer aided design 389 -396

2014
GLADE: a modern global router considering layer directives

Yen-Jung Chang , Tsung-Hsien Lee , Ting-Chi Wang
international conference on computer aided design 319 -323

12
2010
NTHU-Route 2.0: a fast and stable global router

Yu-Ting Lee , Yen-Jung Chang , Ting-Chi Wang
international conference on computer aided design 338 -343

98
2008
Mask-cost-aware ECO routing

Hsi-An Chien , Yun-Ru Wu , Hsin-Chang Lin , Ting-Hsiung Wang
design, automation, and test in europe 1 -4

1
2014
Metal layer planning for silicon interposers with consideration of routability and manufacturing cost

Wen-Hao Liu , Tzu-Kai Chien , Ting-Chi Wang
design, automation, and test in europe 1 -6

6
2014
A new global router for modern designs

Jhih-Rong Gao , Pei-Ci Wu , Ting-Chi Wang
asia and south pacific design automation conference 232 -237

50
2008
An MILP-based wire spreading algorithm for PSM-aware layout modification

Yung-Chia Lin , Ming-Chao Tsai , Ting-Chi Wang
asia and south pacific design automation conference 364 -369

3
2008
Blockage-Aware Routing Tree Construction with Concurrent Buffer and Flip-Flop Insertion

Shu-Yun Chen , Ting-Chi Wang
Proceedings of The Workshop on Synthesis And System Integration of Mixed Information technologies, Sapporo, Japan, October 2007 147 -154

4
2007
Routing for Symmetric FPGA's and FPIC's

C. L. Liu , Yachyang Sun , Ting-Chi Wang , C. K. Wong
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 16 ( 1) 20 -31

11
1997
Multiple-Layer Multiple-Patterning Aware Placement Refinement for Mixed-Cell-Height Designs

Wai-Kei Mak , Ting-Chi Wang , Bo-Yang Chen , Chi-Chun Fang
international symposium on physical design 31 -38

2021
RDTA: An Efficient Routability-Driven Track Assignment Algorithm

Genggeng Liu , Zhen Zhuang , Wenzhong Guo , Ting-Chi Wang
great lakes symposium on vlsi 315 -318

2
2019
MiniDeviation: An Efficient Multi-Stage Bus-Aware Global Router

Ting-Chi Wang , Weida Zhu , Xinghai Zhang , Genggeng Liu
international symposium on vlsi design, automation and test 1 -4

1
2020
Optimal post-routing redundant via insertion

Kuang-Yao Lee , Cheng-Kok Koh , Ting-Chi Wang , Kai-Yuan Chao
international symposium on physical design 111 -117

25
2008
An enhanced global router with consideration of general layer directives

Tsung-Hsien Lee , Yen-Jung Chang , Ting-Chi Wang
Proceedings of the 2011 international symposium on Physical design - ISPD '11 53 -60

14
2011
A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree Construction

Pei-Ci Wu , Jhih-Rong Gao , Ting-Chi Wang
asia and south pacific design automation conference 262 -267

30
2007
Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability

Chung-Wei Lin , Ming-Chao Tsai , Kuang-Yao Lee , Tai-Chen Chen
asia and south pacific design automation conference 238 -243

118
2007
Fast Buffered Delay Estimation Considering Process Variations

Tien-Ting Fang , Ting-Chi Wang
asia and south pacific design automation conference 702 -707

2007