作者: Ting-Chi Wang , Weida Zhu , Xinghai Zhang , Genggeng Liu , Wenzhong Guo
DOI: 10.1109/VLSI-DAT49148.2020.9196219
关键词:
摘要: As the number of signal nets increases significantly, global routing buses becomes an increasingly important and difficult problem. In this paper, to match timing buses, we propose efficient multi-stage bus-aware algorithm called MiniDeviation that is based on several techniques: 1) a deviation-driven segment shifting, 2) double maze strategy, 3) post-routing scheme. Compared with existing algorithms, experimental results show proposed router achieves best for both total wirelength deviation overflow.