Routing for Symmetric FPGA's and FPIC's

摘要: A new class of routing structures with fixed orthogonal wire segments and field programmable switches at the intersections is proposed. In comparison conventional two-dimensional field-programmable gate array (FPGA) structure, this has advantage using a smaller number active switches. An existing interconnect chip (EPIC) structure can be included as special case in our structures. Using probabilistic model, we prove that complete achieved high degree probability which tracks each channel approaches lower bound asymptotically. We present sequential algorithm based on solution single net problem. take into account delay introduced by path formulate problem node-weighted Steiner minimum tree (NWSMT) bipartite graph G. Since NP-complete, polynomial time approximate produces an optimal for some classes graphs. general, obtained performance min{Δ(V\Z,|Z|-1}. addition, also it NP-complete to determine approximates within any constant bound. Experimental results several industrial circuits show reduction up 41% when compared corresponding FPGA structure.