Postgrid Clock Routing for High Performance Microprocessor Designs
作者： Haitong Tian , Wai-Chung Tang , Evangeline F. Y. Young , C. N. Sze
DOI: 10.1109/TCAD.2011.2170688
关键词: Clock skew 、 Engineering 、 Synchronous circuit 、 Underclocking 、 CPU multiplier 、 Clock gating 、 Clock network 、 Clock rate 、 Digital clock manager 、 Electronic engineering
摘要: Designing a high-quality clock network is very important in large-scale integrated designs today, as it the that synchronizes all elements of chip, and also major source power dissipation system. Early study by Pham 2006 shows about 18.1% total capacitance was due to this postgrid routing (i.e., lower mesh wires plus twig wires). In paper, we proposed partition-based path expansion algorithm solve problem effectively. Experimental results on industrial test cases show our can improve over latest work Shelar significantly reducing wire 24.6% wirelength 23.6%.
sci-hub.se 参考文章(11)
K.D. Boese, A.B. Kahng, Zero-skew clock routing trees with minimum wirelength international conference on asic. pp. 17- 21 ,(1992) , 10.1109/ASIC.1992.270316
Chung-Kuan Cheng, Bo Yao, Hongyu Chen, Makoto Mori, A mulitple level network approach for clock skew minimization with process variations asia and south pacific design automation conference. pp. 263- 268 ,(2004) , 10.5555/1015090.1015152
D.C. Pham, T. Aipperspach, D. Boerstler, M. Bolliger, R. Chaudhry, D. Cox, P. Harvey, P.M. Harvey, H.P. Hofstee, C. Johns, J. Kahle, A. Kameyama, J. Keaty, Y. Masubuchi, M. Pham, J. Pille, S. Posluszny, M. Riley, D.L. Stasiak, M. Suzuoki, O. Takahashi, J. Warnock, S. Weitzel, D. Wendel, K. Yazawa, Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor IEEE Journal of Solid-State Circuits. ,vol. 41, pp. 179- 196 ,(2006) , 10.1109/JSSC.2005.859896
Rupesh S. Shelar, An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors Proceedings of the 2009 international symposium on Physical design - ISPD '09. pp. 141- 148 ,(2009) , 10.1145/1514932.1514964
P.K. Chan, K. Karplus, Computing signal delay in general RC networks by tree/link partitioning IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 9, pp. 898- 902 ,(1990) , 10.1109/43.57781
P.J. Restle, T.G. McNamara, D.A. Webber, P.J. Camporese, K.F. Eng, K.A. Jenkins, D.H. Allen, M.J. Rohn, M.P. Quaranta, D.W. Boerstler, C.J. Alpert, C.A. Carter, R.N. Bailey, J.G. Petrovick, B.L. Krauter, B.D. McCredie, A clock distribution network for microprocessors IEEE Journal of Solid-state Circuits. ,vol. 36, pp. 792- 799 ,(2001) , 10.1109/4.918917
Andrew Kahng, Jason Cong, Gabriel Robins, High-performance clock routing based on recursive geometric matching design automation conference. pp. 322- 327 ,(1991) , 10.1145/127601.127688
Rupesh S. Shelar, Routing With Constraints for Post-Grid Clock Distribution in Microprocessors IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 29, pp. 245- 249 ,(2010) , 10.1109/TCAD.2009.2040012
R.-S. Tsay, An exact zero-skew clock routing algorithm IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 12, pp. 242- 249 ,(1993) , 10.1109/43.205004
Haitong Tian, Wai-Chung Tang, Evangeline F.Y. Young, C.N. Sze, Grid-to-ports clock routing for high performance microprocessor designs Proceedings of the 2011 international symposium on Physical design - ISPD '11. pp. 21- 28 ,(2011) , 10.1145/1960397.1960406