Grid-to-ports clock routing for high performance microprocessor designs

摘要: Clock distribution in VLSI designs is of crucial importance and it also a major source power dissipation system. For today's high performance microprocessors, clock signals are usually distributed by global grid covering the whole chip, followed post-grid routing that connects loads to grid. Early study [2] shows about 18.1% total capacitance was due this (i.e., lower mesh wires plus twig wires). This problem thus an important one but not many previous works have addressed it. In paper, we try solve connecting ports through reserved tracks on multiple metal layers, with delay slew constraints. Note set for grid-to-ports practice because conventional modular design style high-performance microprocessors. We propose new expansion algorithm based heap data structure effectively. Experimental results industrial test cases show our can improve over latest work [1] significantly reducing 24.6% wire length 23.6%. validate using hspice simulation. Finally, approach very efficient larger 2000 ports, runtime seconds.