引用次数
引用: 2,593
H-指数: 27
I10-指数 : 59
出版物: 184
Shedding physical synthesis area bloat
Ying Zhou , Charles J Alpert , Zhuo Li , Cliff Sze
Vlsi Design 2011 2
4
2011
Physical Synthesis with Clock-Network Optimization for Large Systems on Chips
David Papa , Charles Alpert , Cliff Sze , Zhuo Li
IEEE Micro 31 ( 4) 51 -62
38
2011
GPU acceleration for Bayesian control of Markovian genetic regulatory networks
He Zhou , Jiang Hu , Sunil P. Khatri , Frank Liu
ieee embs international conference on biomedical and health informatics 304 -307
3
2016
Guiding a physical design closure system to produce easier-to-route designs with more predictable timing
Zhuo Li , Charles J Alpert , Gi-Joon Nam , Cliff Sze
Proceedings of the 49th Annual Design Automation Conference on - DAC '12 465 -470
15
2012
The DAC 2012 routability-driven placement contest and benchmark suite
Natarajan Viswanathan , Charles Alpert , Cliff Sze , Zhuo Li
Proceedings of the 49th Annual Design Automation Conference on - DAC '12 774 -782
61
2012
GLARE
Yaoguang Wei , Cliff Sze , Natarajan Viswanathan , Zhuo Li
Proceedings of the 49th Annual Design Automation Conference on - DAC '12 768 -773
68
2012
PACMAN: Driving Nonuniform Clock Grid Loads for low-skew robust clock network
Nancy Y Zhou , Phillip Restle , Joseph Palumbo , Joseph Kozhaya
system level interconnect prediction 1 -5
4
2014
ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite
Natarajan Viswanathan , Charles Alpert , Cliff Sze , Zhuo Li
international conference on computer aided design 345 -348
33
2012
Techniques for scalable and effective routability evaluation
Yaoguang Wei , Cliff Sze , Natarajan Viswanathan , Zhuo Li
ACM Transactions on Design Automation of Electronic Systems 19 ( 2) 17
5
2014
Ultra-fast interconnect driven cell cloning for minimizing critical path delay
Zhuo Li , David A Papa , Charles J Alpert , Shiyan Hu
international symposium on physical design 75 -82
4
2010
The future of clock network synthesis
Cliff Sze
international conference on computer aided design
1
2011
Fast and Highly Scalable Bayesian MDP on a GPU Platform
He Zhou , Sunil P. Khatri , Jiang Hu , Frank Liu
international conference on bioinformatics 158 -167
3
2017
Routing congestion estimation with real design constraints
Wen-Hao Liu , Yaoguang Wei , Cliff Sze , Charles J Alpert
design automation conference 92
18
2013
The nuts and bolts of physical synthesis
Charles J Alpert , Shrirang Karandikar , Zhuo Li , Gi-Joon Nam
system-level interconnect prediction 89 -94
3
2007
16 Scaling with Design Constraints: Predicting the Future of Big Chips Wei Huang, Karthick Rajamani, Mircea R. Stan, and Kevin Skadron 30 Rigel: A 1,024-Core Single-Chip Accelerator
Daniel R Johnson , Matthew R Johnson , John H Kelm , William Tuohy
Smpte Journal
2011
Vassilios Chouliaras, Loughborough Univ., UK
Koushik K Das , Alex Doboli , Ahmet Erdogan , Eby G Friedman
Wrip: logic restructuring techniques for wirelength-driven incremental placement
Xing Wei , Wai-Chung Tang , Yu-Liang Wu , Cliff Sze
327 -332
3
2012
an Intuitive Logic Shifting Heuristic for Improving Timing Slack Violating Paths
Xing Wei , Wai-Chung Tang , Yu-Liang Wu , Cliff Sze