Techniques for scalable and effective routability evaluation

作者: Yaoguang Wei , Cliff Sze , Natarajan Viswanathan , Zhuo Li , Charles J Alpert

DOI: 10.1145/2566663

关键词:

摘要: Routing congestion has become a critical layout challenge in nanoscale circuits since it is factor determining the routability of design. An unroutable design not useful even though closes on all other metrics. Fast closure can only be achieved by accurately evaluating whether routable or early cycle. Lately, common to use “light mode” version global router quickly evaluate given placement. This approach suffers from three weaknesses: (i) does adequately model local routing resources, which cause incorrect predictions that are detected late, during detailed routing; (ii) maps obtained tend have isolated hotspots surrounded noncongested spots, called “noisy hotspots”, further affects accuracy evaluation; and (iii) metrics used represent may yield numbers do provide sufficient intuition designer, moreover, they often fail predict accurately. article presents solutions these issues. First, we propose approaches resources. Second, smoothing technique reduce number noisy obtain more accurate evaluation result. Finally, develop new metric represents with higher fidelity. We apply proposed techniques several industrial demonstrate one better mitigation tools perform much improve routability.

参考文章(45)
Min Pan, Chris Chu, IPR: an integrated placement and routing algorithm design automation conference. pp. 59- 62 ,(2007) , 10.1145/1278480.1278496
Yoshua Bengio, James Bergstra, Random search for hyper-parameter optimization Journal of Machine Learning Research. ,vol. 13, pp. 281- 305 ,(2012)
Jinan Lou, S. Thakur, S. Krishnamoorthy, H.S. Sheng, Estimating routing congestion using probabilistic analysis IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 21, pp. 32- 41 ,(2002) , 10.1109/43.974135
A.B. Kahng, Qinke Wang, Implementation and extensibility of an analytic placer IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 24, pp. 734- 747 ,(2005) , 10.1109/TCAD.2005.846366
Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan, An integrated nonlinear placement framework with congestion and porosity aware buffer planning design automation conference. pp. 702- 707 ,(2008) , 10.1145/1391469.1391651
C. Chu, Yiu-Chung Wong, FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 27, pp. 70- 83 ,(2008) , 10.1109/TCAD.2007.907068
A.E. Eiben, S.K. Smit, Parameter tuning for configuring and analyzing evolutionary algorithms Swarm and evolutionary computation. ,vol. 1, pp. 19- 31 ,(2011) , 10.1016/J.SWEVO.2011.02.001
David Z. Pan, Kun Yuan, Katrina Lu, Minsik Cho, BoxRouter 2.0: architecture and implementation of a hybrid and robust global router international conference on computer aided design. pp. 503- 508 ,(2007) , 10.5555/1326073.1326176
Min Pan, Chris Chu, FastRoute: a step to integrate global routing into placement international conference on computer aided design. pp. 464- 471 ,(2006) , 10.1145/1233501.1233596
Szu-Jui Chou, Huang-Yu Chen, Sheng-Lung Wang, Yao-Wen Changt, Novel wire density driven full-chip routing for CMP variation control international conference on computer aided design. pp. 831- 838 ,(2007) , 10.5555/1326073.1326247