Accurate estimation of global buffer delay within a floorplan

摘要: Closed-form expressions for buffered interconnect delay approximation have been around some time. However, previous approaches assume that buffers are free to be placed anywhere. In practice, designs frequently large blocks make the ideal buffer-insertion solution unrealizable. The theory of Otten (ACM/IEEE Intl. Symp. Physical Design, p. 104, 1998) is extended show how one can model into a simple delay-estimation technique applies both two-pin and multipin nets. Even though formula uses buffer type, it shows remarkable accuracy in predicting when compared an optimal realizable solution. Potential applications include wire planning, timing analysis during floorplanning, or global routing. authors' experiments their approach accurately predicts constructing insertion with multiple types