Optimal circuit clustering with variable interconnect delay

摘要: The paper aims at extending the circuit clustering algorithm of Rajaraman and Wong (1995) to handle a more sophisticated delay model, which practically takes variable interconnect into account. Our model is particularly applicable in allowing back-annotation actual information drive process. We first show that original fails produce optimal solutions for this model. In order solve problem, generalized based on an extension proposed such problem can be solved optimally while polynomial time complexity maintained.