CATALYST: planning layer directives for effective design closure

摘要: For the last several technology generations, VLSI designs in new nodes have had to confront challenges associated with reduced scaling wire delays. The solution from industrial back-end-of-line process has been add more and thick metal layers wiring stacks. However, existing physical synthesis tools are usually not effective handling these for design closure. To fully leverage degrees of freedom, it is essential flow provide better communication among timer, router, different optimization engines. This work proposes a algorithm, CATALYST, perform congestion- timing-aware layer directive assignment. Our balances routing resources stacks so that benefit availability by achieving improved timing buffer usage reduction while maintaining routability. Experiments demonstrate effectiveness proposed algorithm.